From Academic Kids

For the town in California, see Montecito, California.

Montecito is the code-name of the next major release of Intel's Itanium Processor Family (IPF), which implements the IA-64 instruction set architecture:

Expected Features and Attributes:

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Die photo
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Die description
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Die power
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Core power breakdown
  • Two cores per die
  • 2-way coarse-grained multithreading per core (not simultaneous). Montecito-flavour of multi-threading is dubbed temporal, or TMT. The two separate threads do not run simultaneously, but the core switches thread in case of a high latency event, like an L3 cache miss which would otherwise stall execution. By this technique, database-like workloads should improve by 15-35 %.
  • a total of 4 threads per die
  • separate 1 MB Instruction L2 and 256 KB Data L2 per core, improved hierarchy
  • 24 MB L3 per die
  • 1.72 billion transistors per die, which is added up from core logic - 57M, or 28,5M per core // core caches - 106.5M // 24 MB L3 cache - 1550M // bus logic & I/O - 6.7M
  • Die size is 27.72 mm x 21.5 mm, or 596 mm²
  • Clock speeds between 2.0 GHz and 2.5 GHz (dynamically variable/top-of-the-line model). The maximum Montecito's design is validated for is 2.5 GHz, but it's more likely that it will actually top out around 2.2 GHz.
  • Advanced clock scaling technology for power management — the clock rate is not fixed, but adjusted to a nominal power envelope. That means that clock and voltage are adjusted to keep the chips consumption within the envelope. Depending on the actual usage pattern the chip will be able to scale up or down, feeding the core with proper voltage. Under so called low activity workloads which generate less heat while being executed Montecito speeds up till it reaches the target power, and vica versa, extreme activity loads may cause the chip to reduce clock rate and core voltage. According to insider sources the nominal power envelope can be adjusted from software. Low-activity workloads are rather integer-intensive computations, mostly commercial, database applications. They should be boosted by around a factor of 10 % compared to a "fixed clock" scenario. High activity workloads are rather floating point-intensive computations, like scientific and R&D simulations. Nominal clock speeds of chips might be based on power drained by these intensive computations. This is Foxton technology. Foxton's clock scaling can be disabled if required.
  • Lower power consumption and thermal dissipation than earlier flagship Itaniums, despite the high transistor count and higher clock speeds; 100 W has been suggested. This is mainly achieved by applying different types of transistors. By default, slower and low-leakage transistor were used, while high-speed, thus high-leakage ones where it was necessary.
  • Demand Base Switching — power saving feature. Dynamically reduces processor power consumption based on demand or load. Works in conjunction with the OS. Could reduce server power consumption for typical CPU utilization.
  • Advanced compensation for errors in cache, for reliable operation under mission-critical workloads. This is Pellston technology.
  • Virtualization technology allowing multiple OS instances per chip. This is Silvervale technology.
  • Improved, higher bandwidth front side bus (FSB), with three times the capacity of the existing bus design. What is not known yet is whether it meant to be at device level (per die) or at system level (per node, with 4 dies). System throughput per node will be at least 21 GB/s.
  • Will also be available with legacy FSB for upgrading existing system designs
  • 90 nanometer design
  • Under evaluation by major OEMs
  • Commercial launch: 2005 H2
  • Volume: 2006
  • In contrast to earlier speculations, there will be no 65 nm shrink, but the codename Montvale will cover a Montecito on-steroids, released one year later, tail end of 2006. Montvale's clock speed will likely hit 2.5 GHz. It is also very likely, that like Montecito, Montvale will also bring an update of the compiler technology, with significant improvement in performance characteristics to IPF. Montvale's successor is Tukwilla, the first 65 nm design, due to 2007. Consisting of at least 4 cores, which will likely be microachitecturally the same as Montecito's ones, it will fit into the so called Common Serial Interconnect, dubbed CSI, a cross-platform with Xeons. A major advancement is not expected till Poulson, which is very little known about this time.

Montecito is also the name of the fictional hotel in the NBC television series Las Vegas.



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